View MB90F352_250533.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13737-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90350 Series MB90F352/S, MB90352/S
s DESCRIPTION
The MB90350-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed for automotive and industrial applications. Its main feature is the on-board CAN Interface, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 m CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 128 Kbytes. An internal voltage booster removes the necessity for a second programming voltage. An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features a 4 channel Output Compare Unit and 6 channel Input Capture Unit with 2 separate 16-bit free running timers. 2 channels UART constitute additional functionality for communication purposes. * : Controller Area Network (CAN) - License of Robert Bosch GmbH Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
s PACKAGE
64-pin Plastic LQFP
(FPT-64P-M09)
MB90350 Series
s FEATURES
* Clock * Built-in PLL clock frequency multiplication circuit * Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz). * Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without S-suffix only) * Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied PLL clock). * Built-in clock modulation circuit * 16 Mbyte CPU memory space * 24-bit internal addressing * External Bus Interface * 4 MByte external memory space * Instruction system best suited to controller * Wide choice of data types (bit, byte, word, and long word) * Wide choice of addressing modes (23 types) * Enhanced multiply-divide instructions and RETI instructions * Enhanced high-precision computing with 32-bit accumulator * Instruction system compatible with high-level language (C language) and multitask * Employing system stack pointer * Enhanced various pointer indirect instructions * Barrel shift instructions * Increased processing speed * 4-byte instruction queue * Powerful interrupt function * Powerful 8-level, 34-condition interrupt feature * Up to 8 channels external interrupts are supported * Automatic data transfer function independent of CPU * Extended intelligent I/O service function (EI2OS) : up to 16 channels * DMA : up to 16 channels * Low power consumption (standby) mode * Sleep mode (a mode that halts CPU operating clock) * Main timer mode (a timebase timer mode switched from the main clock mode) * PLL timer mode (a timebase timer mode switched from the PLL clock mode) * Watch mode (a mode that operates sub clock and clock timer only) * Stop mode (a mode that stops oscillation clock and sub clock) * CPU blocking operation mode * Process * CMOS technology * I/O port * General-purpose input/output port (CMOS output) - 49 ports (devices without S-suffix) - 51 ports (devices with S-suffix)
(Continued)
2
MB90350 Series
(Continued)
* Timer * Time-base timer, clock timer, watchdog timer : 1 channel * 8/16-bit PPG timer : 8-bit x 10 channels, or 16-bit x 6 channels * 16-bit reload timer : 4 channels * 16- bit input/output timer - 16-bit free run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7) - 16- bit input capture: (ICU) : 6 channels - 16-bit output compare : (OCU) : 4 channels * Full-CAN interface : 1 channel * Compliant with Ver2.0A and Ver2.0B CAN specifications * Flexible message buffering (mailbox and FIFO buffering can be mixed) * CAN wake-up function * UART (LIN/SCI) : 2 channels * Equipped with full-duplex double buffer * Clock-asynchronous or clock-synchronous serial transmission is available * I2C interface* : 1 channel * Up to 400 Kbit/s transfer rate * DTP/External interrupt : 8 channels, CAN wakeup : 1 channel * Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt. * Delay interrupt generator module * Generates interrupt request for task switching. * 8/10-bit A/D converter : 15 channels * Resolution is selectable between 8-bit and 10-bit. * Activation by external trigger input is allowed. * Conversion time : 3 s (at 24-MHz machine clock, including sampling time) * Program patch function * Address matching detection for 6 address pointers. * Internal voltage regulator * Supports 3 V MCU core, offering low EMI and low power consumption figures * Programmable input levels * Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode) * TTL level (initial level for External bus mode) * Flash security function * Protects the content of Flash (Flash device only) * : I2C license : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
3
MB90350 Series
s PRODUCT LINEUP
Part Number MB90F352/S, MB90352/S*1 Parameter CPU System clock ROM RAM Emulator-specific power supply*2 Technology Operating voltage range Temperature range Package F2MC-16LX CPU On-chip PLL clock multiplier (x1, x2, x3, x4, x6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz osc. PLL x 6) Boot-block, Flash memory 128 Kbytes 4 Kbytes 0.35 m CMOS with regulator for internal power supply + Flash memory charge pump for programming voltage 3.5 V - 5.5 V : at normal operating (not using A/D converter) 4.0 V - 5.5 V : at using A/D converter/Flash programming 4.5 V - 5.5 V : at using external bus -40 C to +105 C (125 C up to 16 MHz machine clock) LQFP-64 2 channels UART External 30 Kbytes Yes 0.35 m CMOS with regulator for internal power supply 5 V 10% PGA-299 3 channels MB90V340A-101/102
Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 1 channel 15 channels 10-bit or 8-bit resolution Conversion time : Min 3 s include sample time (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (Channel 0, 4) Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1 I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7 Signals an interrupt when 16-bit I/O Timer match output compare registers. A pair of compare registers can be used to generate an output signal. Rising edge, falling edge or rising & falling edge sensitive Signals an interrupt upon external event 1 channel
I2C (400 kbit/s) A/D Converter 16-bit Reload Timer (4 channels) 16-bit I/O Timer (2 channels) 16-bit Output Compare (4 channels) 16-bit Input Capture (6 channels)
(Continued)
4
MB90350 Series
Part Number MB90F352/S, MB90352/S*1 Parameter Supports 8-bit and 16-bit operation modes 8-bit reload counters x 12 8/16-bit 8-bit reload registers for L pulse width x 12 Programmable Pulse 8-bit reload registers for H pulse width x 12 Generator A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 6 channels (16-bit) / 8-bit prescaler + 8-bit reload counter 10 channels (8-bit) Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) 1 channel Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps Can be used rising edge, falling edge, starting up by H/L level input, external interrupt, extended intelligent I/O services (EI2OS) and DMA devices with `S'-suffix and MB90V340A-102 : without subclock devices without `S'-suffix and MB90V340A-101 : with subclock Virtually all external pins can be used as general purpose I/O port All push-pull outputs Bit-wise settable as input/output or peripheral signal Settable as CMOS schmitt trigger/ automotive inputs (default) TTL input level settable for external bus (30 terminals only for external bus) Supports automatic programming, Embedded AlgorithmTM*3 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash 1 channel 2 channels MB90V340A-101/102
CAN Interface
External Interrupt (8 channels) D/A converter Subclock (up to100 kHz)
I/O Ports
Flash Memory
*1 : The devices are under development. *2 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the Emulator hardware manual about details. *3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90350 Series
s PIN ASSIGNMENTS
* MB90F352/S, MB90352/S (TOP VIEW) (LQFP-64P)
P12/AD10/SIN3/INT11R
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P23/A19/PPGF(E)
P20/A16/PPG9(8)
P14/AD12/SCK3
P13/AD11/SOT3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vcc C P25/A21/IN1/ADTG P44/SDA0/FRCK0 P45/SCL0/FRCK1 P30/ALE/IN4 P31/RD/IN5 P32/WRL/WR/INT10R P33/WRH P34/HRQ/OUT4 P35/HAK/OUT5 P36/RDY/OUT6 P37/CLK/OUT7 P60/AN0 P61/AN1 AVcc
P11/AD09/TOT1
P24/A20/IN0
P17/AD15
P16/AD14
P15/AD13
RST
Vss
X0
X1
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P63/AN3/PPG6(7) P54/AN12/TOT3 P51/AN9/SOT2 AVRH P50/AN8/SIN2 P62/AN2/PPG4(5) P64/AN4/PPG8(9) P65/AN5/PPGA(B) P66/AN6/PPGC(D) P67/AN7/PPGE(F) P55/AN13
AV ss
P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 P04/AD04/INT12 P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 MD0 MD1 MD2 P41/X1A* P40/X0A* Vss P43/IN7/TX1
P 52/A N 10/S C K 2
P 5 6 /A N 1 4
(FPT-64P-M09) * : MB90F352/352 : X0A, X1A MB90F352S/352S : P40, P41
6
P 4 2 /IN 6 /R X 1 /IN T 9 R
P 53/A N 11/TIN 3
MB90350 Series
s PIN DESCRIPTION
Pin No. LQFP64* 46 47 45 Pin name X1 X0 RST P62 to P67 3 to 8 AN2 to AN7 PPG4, 6, 8, A, C, E P50 9 AN8 SIN2 P51 10 AN9 SOT2 P52 11 AN10 SCK2 P53 12 AN11 TIN3 P54 13 AN12 TOT3 14, 15 P55, P56 AN13, AN14 P42 16 IN6 RX1 INT9R P43 17 IN7 TX1 P40, P41 19, 20 X0A, X1A B F F F I I I I I O I Circuit type A E Oscillation output pin. Oscillation input pin. Reset input pin. General purpose I/O ports. Analog input pins for A/D converter. Output pins for PPGs. General purpose I/O port. Analog input pin for A/D converter. Serial data input pin for UART2. General purpose I/O port. Analog input pin for A/D converter. Serial data output pin for UART2. General purpose I/O port. Analog input pin for A/D converter. Serial data output pin for UART2. General purpose I/O port. Analog input pin for A/D converter. Event input pin for reload timer3. General purpose I/O port. Analog input pin for A/D converter. Output pin for reload timer3. General purpose I/O ports. Analog input pins for A/D converter. General purpose I/O port. Data sample input pin for input capture ICU6. RX input pin for CAN1. External interrupt request input pin for INT9. General purpose I/O port. Data sample input pin for input capture ICU7. TX output pin for CAN1. General purpose I/O ports (devices with S-suffix and MB90V340A-101) . Oscillation input pins for sub clock (devices without S-suffix and MB90V340A-102) . Function
(Continued)
7
MB90350 Series
Pin No. LQFP64*
Pin name P00 to P07
Circuit type
Function General purpose I/O ports.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode.
24 to 31
AD00 to AD07 INT8 to INT15 P10
G
Input/output pins of external address data bus lower 8 bit. This function is enabled when the external bus is enabled. External interrupt request input pins for INT8 to INT15. General purpose I/O port.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode.
32
AD08 TIN1 P11
G
Input/output pin for external bus address data bus bit 8. This function is enabled when external bus is enabled. Event input pin for reload timer1. General purpose I/O.The register can be set to select whether to use a pull-up resistor.This function is enabled in single-chip mode.
33
AD09 TOT1 P12
G
Input/output pin for external bus address data bus bit 9. This function is enabled when external bus is enabled. Output pin for reload timer1. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
34
AD10 SIN3 INT11R P13
N
Input/output pin for external bus address data bus bit 10. This function is enabled when external bus is enabled. Serial data input pin for UART3. External interrupt request input pin for INT11 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
35
AD11 SOT3 P14
G
Input/output pin for external bus address data bus bit 11. This function is enabled when external bus is enabled. Serial data output pin for UART3. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
36
AD12 SCK3 P15
G
Input/output pin for external bus address data bus bit 12. This function is enabled when external bus is enabled. Clock input/output pin for UART3. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 13. This function is enabled when external bus is enabled. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 14. This function is enabled when external bus is enabled.
37 AD13 P16 38 AD14
N
G
(Continued)
8
MB90350 Series
Pin No. LQFP64*
Pin name P17
Circuit type
Function General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 15. This function is enabled when external bus is enabled. General purpose I/O ports. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1.
39 AD15
G
P20 to P23 40 to 43 A16 to A19 PPG9, PPGB, PPGD, PPGF P24 44 A20 IN0 P25 G G
Output pins for A16 to A19 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins A16 to A19. Output pins for PPGs. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. Output pins for A20 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pin is enabled as high address output pins A20. Data sample input pin for input capture ICU0. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1.
51 A21 IN1 ADTG P44 52 SDA0 FRCK0 P45 53 SCL0 FRCK1 P30 54 ALE IN4
G
Output pin for A21 of the external address bus. When the corresponding bit in the external address output control register (HACR) is 0, the pin is enabled as high address output pin A21. Data sample input pin for input capture ICU1. Trigger input pin for A/D converter. General purpose I/O port
H
Serial data I/O pin for I2C 0 Input pin for the 16-bit I/O Timer 0 General purpose I/O port.
H
Serial clock I/O pin for I2C 0 Input for the 16-bit I/O Timer 1 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
G
Address latch enable output pin. This function is enabled when external bus is enabled. Data sample input pin for input capture ICU4.
(Continued)
9
MB90350 Series
Pin No. LQFP64*
Pin name P31
Circuit type
Function General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
55
RD IN5 P32
G
Read strobe output pin for data bus. This function is enabled when external bus is enabled. Data sample input pin for input capture ICU5. General purpose I/O port. The register can be set to select whether to use pull-up resistor. This function is enabled either in single-chip mode or with the WR/WRL pin output disabled.
56 WR/WRL INT10R P33 57 WRH
G
Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit access. External interrupt request input pin for INT10. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the WRH pin output disabled. Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled.
G
P34 58 HRQ OUT4 P35 59 HAK OUT5 P36 60 RDY OUT6 P37 61 CLK OUT7 10 G G G G
Hold request input pin. This function is enabled when both the external bus and the hold function are enabled. Waveform output pin for output compare OCU4. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. Hold acknowledge output pin. This function is enabled when both the external bus and the hold function are enabled. Waveform output pin for output compare OCU5. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the external ready function disabled. Ready input pin. This function is enabled when both the external bus and the external ready function are enabled. Waveform output pin for output compare OCU6. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the CLK output disabled. CLK output pin. This function is enabled when both the external bus and CLK output are enabled. Waveform output pin for output compare OCU7.
(Continued)
MB90350 Series
(Continued) Pin No.
LQFP64* 62, 63 64 2 1 22, 23 21 49 18, 48 50 * : FPT-64P-M09
Pin name P60, P61 AN0, AN1 AVCC AVRH AVSS MD1, MD0 MD2 VCC VSS C
Circuit type I K L K C D K General purpose I/O ports.
Function
Analog input pins for A/D converter. VCC power input pin for analog circuits. Reference voltage input for the A/D converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. VSS power input pin for analog circuits. Input pins for specifying the operating mode. Input pins for specifying the operating mode. Power (3.5 V to 5.5 V) input pin. Power (0 V) input pins. This is the power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 F ceramic capacitor.
11
MB90350 Series
s I/O CIRCUIT TYPE
Type Circuit Remarks Oscillation circuit * High-speed oscillation feedback resistor = approx. 1 M
X1
Xout
A
X0
Standby control signal
X1A
Xout
Oscillation circuit * Low-speed oscillation feedback resistor = approx. 10 M
B
X0A
Standby control signal
Mask ROM device: * CMOS Hysteresis input pin C
R Hysteresis inputs
Flash device: * CMOS input pin Mask ROM device: * CMOS Hysteresis input pin * Pull-down resistor valule: approx. 50 k Flash device: * CMOS input pin * No Pull-down
R Hysteresis inputs
D
Pull-down Resistor
CMOS Hysteresis input pin * Pull-up resistor valule: approx. 50 k E
Pull-up Resistor R Hysteresis inputs
(Continued)
12
MB90350 Series
Type
Circuit
Remarks * CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standby-time input shutdown function)
Pout
Nout
F
R Hysteresis inputs
Automotive inputs Standby control for input shutdown pull-up control pull-up resistor Pout
Nout
G
R Hysteresis inputs
* CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standby-time input shutdown function) * TTL input (With the standby-time input shutdown function) * Programmalble pullup resistor: 50 k approx.
Automotive inputs
TTL input Standby control for input shutdown
Pout
Nout
H
* CMOS level output (IOL = 3 mA, IOH = -3 mA) * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standby-time input shutdown function)
R Hysteresis inputs
Automotive inputs Standby control for input shutdown
(Continued)
13
MB90350 Series
Type
Circuit
Remarks * CMOS level output(IOL = 4 mA) * CMOS hysteresis inputs (With the standby-time input shutdown function) * Automotive input (With the standby-time input shutdown function) * A/D analog input
Pout
Nout R
I
Hysteresis inputs
Automotive inputs Standby control for input shutdown Analog input
* Power supply input protection circuit
K
ANE
L
AVR ANE
* A/D converter reference voltage power supply input pin, with the protection circuit * Flash devices do not have a protection circuit against VCC for pin AVRH
(Continued)
14
MB90350 Series
(Continued) Type
pull-up registor Pout
Circuit
pull-up control
Remarks * CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS inputs (With the standby-time input shutdown function) * Automotive input (With the standby-time input shutdown function) * TTL input (With the standby-time input shutdown function) * Programmable pull-up registor:50 k approx
Nout
N
R CMOS inputs
Automotive inputs
TTL input Standby control for input shutdown
Pout
Nout R
O
* CMOS level output (IOL = 4 mA, IOH = -4 mA) * CMOS inputs (With the standby-time input shutdown function) * Automotive input (With the standby-time input shutdown function) * A/D analog input
CMOS inputs
Automotive inputs Standby control for input shutdown Analog input
15
MB90350 Series
s HANDLING DEVICES
Special care is required for the following when handling the device : * Preventing latch-up * Treatment of unused pins * Using external clock * Precautions for when not using a sub clock signal * Notes on during operation of PLL clock mode * Power supply pins (VCC/VSS) * Pull-up/down resistors * Crystal Oscillator Circuit * Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs * Connection of Unused Pins of A/D Converter * Notes on Energization * Stabilization of power supply voltage * Initialization * Port0 to port3 output during Power-on (External-bus mode) * Notes on using CAN Function * Flash security Function
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than VCC or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VCC and VSS. * The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage.
2. Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open. MB90350 Series X0 Open X1
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open. 16
MB90350 Series
5. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
6. Power supply pins (VCC/VSS)
* If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. * Connect VCC and VSS to the device from the current supply source at a low impedance. * As a measure against power supply noise, connect a capacitor of about 0.1 F as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device Vcc Vss
Vcc Vss Vcc
Vss
MB90350 Series
Vcc Vss
Vss
Vcc
7. Pull-up/down resistors
The MB90350 Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external components where needed.
8. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation.
9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
10. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
17
MB90350 Series
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more s (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power again.
14. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of Port 0 to Port 3 might be unstable.
1/2 VCC VCC
Port0 to Port3
Port0 to Port3 outputs might be unstable Port0 to Port3 outputs = Hi-Z
15. Notes on using CAN Function
To use CAN function, please set '1' to DIRECT bit of CAN Direct Mode Register (CDMR). If DIRECT bit is set to '0' (initial value), wait states will be performed when accessing CAN registers. Please refer to Hardware Manual of MB90350 series for detail of CAN Direct Mode Register.
16. Flash security Function
The security byte is located in the area of the flash memory. If protection code 01H is written in the security bit, the flash memory is in the protected state by security. Therefore please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security bit. Flash memory size MB90F352 Embedded 1 Mbit Flash Memory Address for security bit FE0001H
18
MB90350 Series
s BLOCK DIAGRAMS
* MB90V340A-101/102 X0,X1 X0A,X1A * RST Clock Controller
16LX CPU
RAM 30 K
IO Timer 0 Input Capture 6 ch Output Compare 4 ch
FRCK0
IN7 to IN4, IN1 to IN0 OUT7 to OUT4
Prescaler 3 ch SOT4 to SOT2 SCK4 to SCK2 SIN4 to SIN2 AVCC AVSS AN14 to AN0 AVRH ADTG 10-bit DAC 1 ch 8/16-bit PPG 12/8 ch I2C Interface 1 ch
IO Timer 1
FRCK1
UART 3 ch
CAN Controller 2 ch
RX2 to RX1 TX2 to TX1
16-bit Reload Timer 4 ch
TIN3, TIN1 TOT3, TOT1
10-bit ADC 15 ch AD15 to AD00 FMC-16 Bus A21 to A16 ALE RD External Bus Interface WRL WRH HRQ HAK RDY CLK
DA00
PPGF to PPG8, PPG6, PPG4, PPG2, PPG0 SDA0 SCL0
External Interrupt
INT15 to INT8 (INT11R to INT9R)
DMAC
* : MB90V340A-102 19
MB90350 Series
* MB90F352/S, MB90352/S X0,X1 X0A,X1A* RST Clock Controller
16LX CPU
RAM 4K
IO Timer 0 Input Capture 6 ch
FRCK0
IN7 to IN4, IN1, IN0 OUT7 to OUT4
ROM/Flash 128 K
Output Compare 4 ch IO Timer 1
Prescaler 2 ch SOT3, SOT2 SCK3, SCK2 SIN3, SIN2 AVCC AVSS AN14 to AN0 AVRH FMC-16 Bus ADTG
FRCK1
UART 2 ch
CAN Controller 1 ch
RX1 TX1
16-bit Reload Timer 4 ch
TIN3, TIN1 TOT3, TOT1
10-bit ADC 15 ch AD15 to AD00 A21 to A16 ALE RD External Bus Interface WRL WRH HRQ HAK RDY CLK INT15 to INT8 (INT11R to INT9R)
PPGF to PPG8 PPG6, PPG4 SDA0 SCL0
8/16-bit PPG 10/6 ch I2C Interface 1 ch External Interrupt
DMAC
* : Only for devices without `S' Suffix
20
MB90350 Series
s MEMORY MAP
MB90V340A-101/102
FFFFFFH FF0000H FEFFFFH FFFFFFH FF0000H FEFFFFH
MB90F352/S MB90352/S ROM (FF bank) ROM (FE bank)
ROM (FF bank) ROM (FE bank)
FE0000H FDFFFFH
FE0000H FDFFFFH
External access area
C00100H C000FFH
00FFFFH 008000H 007FFFH 007900H 0078FFH
ROM (image of FF bank) Peripheral
00FFFFH 008000H 007FFFH 007900H
ROM (image of FF bank) Peripheral
RAM 30 K
001100H 0010FFH
RAM 4 K
000100H 0000EFH 000000H 000100H
External access area
Peripheral
0000EFH 000000H
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible only in bank FF.
21
MB90350 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H to 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H to 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H to 37H 38H 39H 3AH 3BH PPG 4 Operation Mode Control Register PPG 5 Operation Mode Control Register PPG 45 Clock Select Register Program Address Detection Control Status Register 1 Port 0 Pull-up Control Register Port 1 Pull-up Control Register Port 2 Pull-up Control Register Port 3 Pull-up Control Register SIN input Level Setting Register Input Level Select Register 0 Input Level Select Register 1 Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Port 3 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Analog Input Enable Register 5 Analog Input Enable Register 6 Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 Reserved ADER5 ADER6 Reserved ILSR0 ILSR1 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 Reserved DDRA Reserved PUCR0 PUCR1 PUCR2 PUCR3 Reserved PPGC4 PPGC5 PPG45 PACSR1 W, R/W W, R/W R/W R/W Address Match Detection 1 16-bit Programable Pulse Generator 4/5 0X000XX1 0X000001 000000X0 00000000 R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 00000000 00000000 00000000 00000000 W UART2, UART3 X00XXXXX R/W R/W R/W R/W R/W R/W R/W R/W R/W Ports Ports Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 00000000 00000000 00000000 00000000 XX000000 00000000 XX000000 XX000000 00000000 R/W R/W Port 5, A/D Port 6, A/D 11111111 11111111 Access R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
22
MB90350 Series
Address 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H, 53H 54H 55H 56H 57H 58H to 5BH 5CH 5DH
Register PPG 6 Operation Mode Control Register PPG 7 Operation Mode Control Register PPG 67 Clock Select Register PPG 8 Operation Mode Control Register PPG 9 Operation Mode Control Register PPG 89 Clock Select Register PPG A operation mode control register PPG B operation mode control register PPG AB clock select register PPG C Operation Mode Control Register PPG D Operation Mode Control Register PPG CD Clock Select Register PPG E Operation Mode Control Register PPG F Operation Mode Control Register PPG EF Clock Select Register Input Capture Control Status Register 0/1 Input Capture Edge Register 0/1 Input Capture Control Status Register 4/5 Input Capture Edge Register 4/5 Input Capture Control Status Register 6/7 Input Capture Edge Register 6/7 Output Compare Control Status Register 4 Output Compare Control Status Register 5
Abbreviation PPGC6 PPGC7 PPG67 Reserved PPGC8 PPGC9 PPG89 Reserved PPGCA PPGCB PPGAB Reserved PPGCC PPGCD PPGCD Reserved PPGCE PPGCF PPGEF Reserved ICS01 ICE01 Reserved ICS45 ICE45 ICS67 ICE67 Reserved OCS4 OCS5
Access W, R/W W, R/W R/W W, R/W W, R/W R/W W, R/W
Resource name 16-bit Programable Pulse Generator 6/7
Initial value 0X000XX1 0X000001 000000X0 0X000XX1
16-bit Programable Pulse Generator 8/9
0X000001 000000X0 0X000XX1 0X000001 000000X0 0X000XX1
16-bit Programable W, R/W Pulse Generator A/B R/W W,R/W W,R/W R/W W,R/W W,R/W R/W 16-bit Programable Pulse Generator E/F 16-bit Programable Pulse Generator C/D
0X000001 000000X0 0X000XX1 0X000001 000000X0
R/W R/W, R
Input Capture 0/1
00000000 XXX0X0XX
R/W R R/W R/W, R
Input Capture 4/5
00000000 XXXXXXXX
Input Capture 6/7
00000000 XXX000XX
R/W Output Compare 4/5 R/W
0000XX00 0XX00000
(Continued)
23
MB90350 Series
Address 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H to 7FH 90H to 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H, A3H A4H
Register Output Compare Control Status Register 6 Output Compare Control Status Register 7 Timer Control Status Register 0 Timer Control Status Register 0 Timer Control Status Register 1 Timer Control Status Register 1 Timer Control Status Register 2 Timer Control Status Register 2 Timer Control Status Register 3 Timer Control Status Register 3 A/D Control Status Register 0 A/D Control Status Register 1 Data Register 0 Data Register 1 A/D Setting Register 0 A/D Setting Register 1 ROM Mirroring Register
Abbreviation OCS6 OCS7 TMCSR0 TMCSR0 TMCSR1 TMCSR1 TMCSR2 TMCSR2 TMCSR3 TMCSR3 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1
Access R/W
Resource name
Initial value 0000XX00
Output Compare 6/7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W W ROM Mirror A/D Converter 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 0XX00000 00000000 XXXX0000 00000000 XXXX0000 00000000 XXXX0000 00000000 XXXX0000 000XXXX0 0000000X 00000000 XXXXXX00 00000000 00000000 XXXXXXX1
Reserved ROMM Reserved Reserved DMA Descriptor Channel Specification Register DMA Status Register L DMA Status Register H Program Address Detection Control Status Register 0 Delayed Interrupt/Release Low-power Mode Control Register Clock Selection Register DCSR DSRL DSRH PACSR0 DIRR LPMCR CKSCR Reserved DMA Stop Status Register DSSR R/W DMA 00000000 R/W R/W R/W R/W R/W W,R/W R,R/W Address Match Detection 0 Delayed Interrupt Low Power Control Circuit Low Power Control Circuit DMA 00000000 00000000 00000000 00000000 00000000 00011000 11111100
80H to 8FH Reserved for CAN Interface 1. Refer to "s CAN CONTROLLERS"
(Continued)
24
MB90350 Series
Address A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to C9H
Register Automatic Ready Function Selection Register External Address Output Control Register Bus Control Signal Selection Register Watchdog Timer Control Register Timebase Timer Control Register Watch Timer Control Register DMA Enable Register L DMA Enable Register H Flash Control Status Register (Flash Devices only. Otherwise reserved) Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15
Abbreviation ARSR HACR ECSR WDTC TBTC WTC Reserved DERL DERH FMCS Reserved ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Reserved
Access W W W R,W W,R/W R,R/W R/W R/W R,R/W
Resource name
Initial value 0011XX00
External Memory Access Watchdog Timer Time base timer Watch timer
00000000 0000000X XXXXX111 1XX00100 1X001000 00000000 00000000 000X0000
DMA
Flash Memory
W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W Interrupt Control
00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111
(Continued)
25
MB90350 Series
Address CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H to EFH F0H to FFH 7900H to 7907H
Register External Interrupt Request Enable Register 1 External Interrupt Request Register 1 External Interrupt Level Register 1 External Interrupt Level Register 1 External Interrupt Source Select Register PLL/Subclock Control register DMA Buffer Address Pointer L DMA Buffer Address Pointer M DMA Buffer Address Pointer H DMA Control Register I/O Register Address Pointer L I/O Register Address Pointer H Data Counter L Data Counter H Serial Mode Register 2 Serial Control Register 2 Reception/Transmission Data Register 2 Serial Status Register 2 Extended Communication Control Register 2 Extended Status/Control Register 2 Baud Rate Reload Register 20 Baud Rate Reload Register 21
Abbreviation ENIR1 EIRR1 ELVR1 ELVR1 EISSR PSCCR BAPL BAPM BAPH DMACS IOAL IOAH DCTL DCTH SMR2 SCR2 RDR2/ TDR2 SSR2 ECCR2 ESCR2 BGR20 BGR21
Access R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W W,R/W W,R/W R/W R,R/W R,W, R/W R/W R/W R/W
Resource name
Initial value 00000000 XXXXXXXX
External Interrupt 1
00000000 00000000 00000000
PLL
XXXX0000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 00000000
DMA
UART2
00001000 000000XX 00000100 00000000 00000000
Reserved External Reserved
(Continued)
26
MB90350 Series
Address 7908H 7909H 790AH 790BH 790CH 790DH 790EH 790FH 7910H 7911H 7912H 7913H 7914H 7915H 7916H 7917H 7918H 7919H 791AH 791BH 791CH 791DH 791EH 791FH 7920H 7921H 7922H 7923H 7924H to 7927H 7928H 7929H 792AH 792BH
Register Reload Register L4 Reload Register H4 Reload Register L5 Reload Register H5 Reload Register L6 Reload Register H6 Reload Register L7 Reload Register H7 Reload Register L8 Reload Register H8 Reload Register L9 Reload Register H9 Reload Register LA Reload Register HA Reload Register LB Reload Register HB Reload Register LC Reload Register HC Reload Register LD Reload Register HD Reload Register LE Reload Register HE Reload Register LF Reload Register HF Input Capture Data Register 0 Input Capture Data Register 0 Input Capture Data Register 1 Input Capture Data Register 1
Abbreviation PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB PRLLC PRLHC PRLLD PRLHD PRLLE PRLHE PRLLF PRLHF IPCP0 IPCP0 IPCP1 IPCP1
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Resource name
Initial value XXXXXXXX
16-bit Programable Pulse Generator 4/5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit Programable Pulse Generator 6/7
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit Programable Pulse Generator 8/9
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit Programable Pulse Generator A/B
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit Programable Pulse Generator C/D
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit Programable Pulse Generator E/F
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Input Capture 0/1
Reserved Input Capture Data Register 4 Input Capture Data Register 4 Input Capture Data Register 5 Input Capture Data Register 5 IPCP4 IPCP4 IPCP5 IPCP5 R R R R Input Capture 4/5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
27
MB90350 Series
Address 792CH 792DH 792EH 792FH 7930H to 7937H 7938H 7939H 793AH 793BH 793CH 793DH 793EH 793FH 7940H 7941H 7942H 7943H 7944H 7945H 7946H 7947H 7948H 7949H 794AH 794BH 794CH 794DH 794EH 794FH
Register Input Capture Data Register 6 Input Capture Data Register 6 Input Capture Data Register 7 Input Capture Data Register 7
Abbreviation IPCP6 IPCP6 IPCP7 IPCP7
Access R R R R
Resource name
Initial value XXXXXXXX
Input Capture 6/7
XXXXXXXX XXXXXXXX XXXXXXXX
Reserved Output Compare Register 4 Output Compare Register 4 Output Compare Register 5 Output Compare Register 5 Output Compare Register 6 Output Compare Register 6 Output Compare Register 7 Output Compare Register 7 Data Register 0 Data Register 0 Control status Register 0 Control status Register 0 Data Register 1 Data Register 1 Control status Register 1 Control status Register 1 Timer Register 0/Reload Register 0 Timer Register 1/Reload Register 1 Timer Register 2/Reload Register 2 Timer Register 3/Reload Register 3 OCCP4 OCCP4 OCCP5 OCCP5 OCCP6 OCCP6 OCCP7 OCCP7 TCDT0 TCDT0 TCCSL0 TCCSH0 TCDT1 TCDT1 TCCSL1 TCCSH1 TMR0/ TMRLR0 TMR1/ TMRLR1 TMR2/ TMRLR2 TMR3/ TMRLR3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 I/O Timer 1 I/O Timer 0 Output Compare 6/7 Output Compare 4/5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 00000000 0XXXXXXX 00000000 00000000 00000000 0XXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
28
MB90350 Series
Address 7950H 7951H 7952H 7953H 7954H 7955H 7956H 7957H 7958H to 796DH 796EH 796FH 7970H 7971H 7972H 7973H 7974H 7975H 7976H 7977H 7978H 7979H, 797AH 797BH 797CH to 79C1H 79C2H 79C3H to 79DFH
Register Serial Mode Register 3 Serial Control Register 3 Reception/Transmission Data Register 3 Serial Status Register 3 Extended Communication Control Register 3 Extended Status/Control Register 3 Baud Rate Reload Register 30 Baud Rate Reload Register 31
Abbreviation SMR3 SCR3 RDR3/ TDR3 SSR3 ECCR3 ESCR3 BGR30 BGR31
Access W, R/W W, R/W R/W R,R/W R,W, R/W R/W R/W R/W
Resource name
Initial value 00000000 00000000 00000000
UART3
00001000 000000XX 00000100 00000000 00000000
Reserved CAN Direct Mode Register I2C Bus Status Register 0 I2C Bus Control Register 0 I2C 10 bit Slave Address Register 0 I2C 10 bit Slave Address Mask Register 0 I C 7 bit Slave Address Register 0 I C 7 bit Slave Address Mask Register 0 I2C data register 0
2 2
CDMR Reserved IBSR0 IBCR0 ITBAL0 ITBAH0 ITMKL0 ITMKH0 ISBA0 ISMK0 IDAR0 Reserved
R/W R W,R/W R/W R/W R/W R/W R/W R/W R/W
CAN clock sync
XXXXXXX0 00000000 00000000 00000000 00000000
I C Interface 0
2
11111111 00111111 00000000 01111111 00000000
I2C Clock Control Register 0
ICCR0 Reserved
R/W
I2C Interface 0
00011111
Clock Modulator Control Register
CMCR Reserved
R,R/W
Clock Modulator
0001X000
(Continued)
29
MB90350 Series
(Continued)
Address 79E0H 79E1H 79E2H 79E3H 79E4H 79E5H 79E6H 79E7H 79E8H 79E9H to 79EFH 79F0H 79F1H 79F2H 79F3H 79F4H 79F5H 79F6H 79F7H 79F8H 79F9H to 7BFFH 7C00H to 7CFFH 7D00H to 7DFFH 7E00H to 7FFFH Program Address Detection Register 3 Program Address Detection Register 3 Program Address Detection Register 3 Program Address Detection Register 4 Program Address Detection Register 4 Program Address Detection Register 4 Program Address Detection Register 5 Program Address Detection Register 5 Program Address Detection Register 5 Register Program Address Detection Register 0 Program Address Detection Register 0 Program Address Detection Register 0 Program Address Detection Register 1 Program Address Detection Register 1 Program Address Detection Register 1 Program Address Detection Register 2 Program Address Detection Register 2 Program Address Detection Register 2 Abbreviation PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 PADR2 PADR2 PADR2 Reserved PADR3 PADR3 PADR3 PADR4 PADR4 PADR4 PADR5 PADR5 PADR5 Reserved Reserved for CAN Interface 1. Refer to "s CAN CONTROLLERS" Reserved for CAN Interface 1. Refer to "s CAN CONTROLLERS" Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 0 Resource name Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Notes : * Initial value of "X" represents unknown value. * Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results reading "X" and any write access should not be performed.
30
MB90350 Series
s CAN CONTROLLERS
The CAN controller has the following features : * Conforms to CAN Specification Version 2.0 Part A and B * Supports transmission/reception in standard frame and extended frame formats * Supports transmitting of data frames by receiving remote frames * 16 transmitting/receiving message buffers * 29-bit ID and 8-byte data * Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask * Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz) List of Control Registers (1) Address CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer enable register Transmit request register Transmit cancel register Transmission complete register Receive complete register Remote request receiving register Receive overrun register Reception interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
31
MB90350 Series
List of Control Registers (2) Address CAN1 007D00H 007D01H 007D02H 007D03H 007D04H 007D05H 007D06H 007D07H 007D08H 007D09H 007D0AH 007D0BH 007D0CH 007D0DH 007D0EH 007D0FH 007D10H 007D11H 007D12H 007D13H 007D14H 007D15H 007D16H 007D17H 007D18H 007D19H 007D1AH 007D1BH Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER Access R/W, W R/W, R R/W R R/W R/W R/W R/W R/W Initial Value 0XXXX0X1 00XXX000 000X0000 XXXXXXXX 00000000 00000000 11111111 X1111111 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX
32
MB90350 Series
List of Message Buffers (ID Registers) (1) Address CAN1 007C00H to 007C1FH 007C20H 007C21H 007C22H 007C23H 007C24H 007C25H 007C26H 007C27H 007C28H 007C29H 007C2AH 007C2BH 007C2CH 007C2DH 007C2EH 007C2FH 007C30H 007C31H 007C32H 007C33H 007C34H 007C35H 007C36H 007C37H 007C38H 007C39H 007C3AH 007C3BH 007C3CH 007C3DH 007C3EH 007C3FH ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX 33 ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX
General-purpose RAM
R/W
MB90350 Series
List of Message Buffers (ID Registers) (2) Address CAN1 007C40H 007C41H 007C42H 007C43H 007C44H 007C45H 007C46H 007C47H 007C48H 007C49H 007C4AH 007C4BH 007C4CH 007C4DH 007C4EH 007C4FH 007C50H 007C51H 007C52H 007C53H 007C54H 007C55H 007C56H 007C57H 007C58H 007C59H 007C5AH 007C5BH 007C5CH 007C5DH 007C5EH 007C5FH ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXX
34
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers) (1) Address CAN1 007C60H 007C61H 007C62H 007C63H 007C64H 007C65H 007C66H 007C67H 007C68H 007C69H 007C6AH 007C6BH 007C6CH 007C6DH 007C6EH 007C6FH 007C70H 007C71H 007C72H 007C73H 007C74H 007C75H 007C76H 007C77H 007C78H 007C79H 007C7AH 007C7BH 007C7CH 007C7DH 007C7EH 007C7FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
35
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers) (2) Address CAN1 007C80H to 007C87H 007C88H to 007C8FH 007C90H to 007C97H 007C98H to 007C9FH 007CA0H to 007CA7H 007CA8H to 007CAFH 007CB0H to 007CB7H 007CB8H to 007CBFH 007CC0H to 007CC7H 007CC8H to 007CCFH 007CD0H to 007CD7H 007CD8H to 007CDFH 007CE0H to 007CE7H 007CE8H to 007CEFH Register Data register 0 (8 bytes) Data register 1 (8 bytes) Data register 2 (8 bytes) Data register 3 (8 bytes) Data register 4 (8 bytes) Data register 5 (8 bytes) Data register 6 (8 bytes) Data register 7 (8 bytes) Data register 8 (8 bytes) Data register 9 (8 bytes) Data register 10 (8 bytes) Data register 11 (8 bytes) Data register 12 (8 bytes) Data register 13 (8 bytes) Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX
DTR0
R/W
DTR1
R/W
DTR2
R/W
DTR3
R/W
DTR4
R/W
DTR5
R/W
DTR6
R/W
DTR7
R/W
DTR8
R/W
DTR9
R/W
DTR10
R/W
DTR11
R/W
DTR12
R/W
DTR13
R/W
36
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers) (3) Address CAN1 007CF0H to 007CF7H 007CF8H to 007CFFH Register Data register 14 (8 bytes) Data register 15 (8 bytes) Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX
DTR14
R/W
DTR15
R/W
37
MB90350 Series
s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause Reset INT9 instruction Exception Reserved Reserved CAN 1 RX / Input Capture 6 CAN 1 TX/NS / Input Capture 7 I2C Reserved 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 PPG 4/5 PPG 6/7 PPG 8/9/C/D PPG A/B/E/F Time Base Timer External Interrupt 8 to 11 Watch Timer External Interrupt 12 to 15 A/D Converter I/O Timer 0 / I/O Timer 1 Input Capture 4/5 Output Compare 4/5 Input Capture 0/1 Output Compare 6/7 Reserved Reserved UART 3 RX UART 3 TX EI2OS clear N N N N N Y1 Y1 N N Y1 Y1 Y1 Y1 N N N N N Y1 N Y1 Y1 N Y1 Y1 Y1 Y1 N N Y2 Y1 DMA ch number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH
(Continued)
38
MB90350 Series
(Continued)
Interrupt cause UART 2 RX UART 2 TX Flash Memory Delayed interrupt Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Notes : * The peripheral resources sharing the ICR register have the same interrupt level. * When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service at a time. * When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O Service, the other one cannot use interrupts. EI2OS clear Y2 Y1 N N DMA ch number 14 15 Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 ICR15 Address 0000BEH 0000BFH
39
MB90350 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage Input voltage Output voltage Maximum Clamp Current Total Maximum Clamp Current "L" level maximum output current "L" level average output current "L" level maximum overall output current "L" level average overall output current "H" level maximum output current "H" level average output current "H" level maximum overall output current "H" level average overall output current AVCC AVRH VI VO ICLAMP |ICLAMP| IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -4.0 Power consumption PD -40 -40 -55 320 +105 +125 +150 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +4.0 40 15 4 100 50 -15 -4 -100 -50 240 Unit V V V V V mA mA mA mA mA mA mA mA mA mA VCC = AVCC*1 AVCC AVRH*1 *2 *2 *4 *4 *3 *3 *3 *3 *3 *3 *3 *3 (VSS = AVSS = 0 V) Remarks
+105 C < TA +125 C, mW Normal operation : maximum frequency 16 MHz -40 C < TA +105 C, mW Normal operation : maximum frequency 24 MHz C C C *5
Operating temperature Storage temperature
TA TSTG
(Continued)
40
MB90350 Series
(Continued)
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67 *4: * Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56 (for evaluation : P50 to P55) , P60 to P67 * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Sample recommended circuits: * Input/output equivalent circuits
Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
*5 : If used exceeding TA = +105 C, be sure to contact Fujitsu for reliability limitations. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
41
MB90350 Series
2. Recommended Conditions
Parameter Symbol Value Min 4.0 Power supply voltage VCC, AVCC 3.5 4.5 3.0 Smooth capacitor CS 0.1 -40 -40 Typ 5.0 5.0 5.0 Max 5.5 5.5 5.5 5.5 1.0 +105 +125 Unit V V V V F C C *
(VSS = AVSS = 0 V) Remarks Under normal operation Under normal operation, when not using the A/D converter and not Flash programming. When External bus is used. Maintains RAM data in stop mode Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor.
Operating temperature
TA
* : If used exceeding TA = +105 C, be sure to contact Fujitsu for reliability limitations.
C
CS
C Pin Connection Diagram
Operation guaranteed range 24
Internal clock fCP (MHz)
16
- 40 Operation temperature TA (C)
105
125
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 42
MB90350 Series
3. DC Characteristics
(TA = -40 C to +105 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 16 MHz, VSS = AVSS = 0 V) Condition Min Value Typ Max VCC + 0.3 Unit Remarks Port inputs if CMOS hysteresis input levels are selected (except P12, P15, P44, P45, P50) Port inputs if AUTOMOTIVE input levels are selected Port inputs if TTL input levels are selected P12, P15, P50 inputs if CMOS input levels are selected P44, P45 inputs if CMOS hysteresis input levels are selected RST input pin (CMOS hysteresis) MD input pin Port inputs if CMOS hysteresis input levels are selected (except P12, P15, P44, P45, P50) Port inputs if AUTOMOTIVE input levels are selected Port inputs if TTL input levels are selected P12, P15, P50 inputs if CMOS input levels are selected P44, P45 inputs if CMOS hysteresis input levels are selected RST input pin (CMOS hysteresis) MD input pin
Parameter
Symbol
Pin
VIHS
0.8 VCC
V
VIHA Input H voltage (At VCC = 5 V 10%) VIHT VIHS

0.8 VCC 2.0 0.7 VCC

VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3
V V V
VIHI VIHR VIHM
0.7 VCC 0.8 VCC VCC - 0.3 VSS - 0.3
V V V
VILS
0.2 VCC
V
VILA Input L voltage (At VCC = 5 V 10%) VILT VILS
Normal outputs I2C current outputs Normal outputs I2C current outputs

VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3

0.5 VCC 0.8 0.3 VCC
V V V
VILI VILR VILM Output H voltage Output H voltage Output L voltage Output L voltage VOH VOHI VOL VOLI
0.3 VCC 0.2 VCC VSS + 0.3 0.4 0.4
V V V V V V V
VSS - 0.3 VCC = 4.5 V, VCC - 0.5 IOH = -4.0 mA VCC = 4.5 V, VCC - 0.5 IOH = -3.0 mA VCC = 4.5 V, IOL = 4.0 mA VCC = 4.5 V, IOL = 3.0 mA
(Continued)
43
MB90350 Series
(Continued)
(TA = -40 C to +105 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 16 MHz, VSS = AVSS = 0 V) Symbol IIL Pin P00 to P07, P10 to P17, P20 to P25, P30 to P37, RST MD2 Condition VCC = 5.5 V, VSS < VI < VCC Value Min -1 Typ Max 1 Unit Remarks A
Parameter Input leak current Pull-up resistance
RUP
25
50
100
k
Pull-down resistance
RDOWN
VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation.
25
50
100
Except k Flash devices mA MB90F352
50
65
ICC
VCC = 5.0 V, Internal frequency : 24 MHz, At writing FLASH memory. VCC = 5.0 V, Internal frequency : 24 MHz, At erasing FLASH memory.
65
80
mA MB90F352
70
85
mA MB90F352
ICCS
VCC = 5.0 V, Internal frequency : 24 MHz, At Sleep mode. VCC = 5.0 V, Internal frequency : 2 MHz, At Main Timer mode VCC VCC = 5.0 V, Internal frequency : 24 MHz, At PLL Timer mode, external frequency = 4 MHz VCC = 5.0 V, Internal frequency: 8 kHz, At sub operation TA = +25C VCC = 5.0 V, Internal frequency: 8 kHz, At sub sleep TA = +25C VCC = 5.0 V, Internal frequency: 8 kHz, At watch mode TA = +25C VCC = 5.0 V, At Stop mode, TA = +25C Other than C, AVCC, AVSS, AVRH, VCC, VSS,
25
35
mA MB90F352
ICTS
0.3
0.8
mA MB90F352
Power supply current*
ICTSPLL6
4
7
mA MB90F352
ICCL
170
360
A MB90F352
ICCLS
20
50
A MB90F352
ICCT
10
35
A MB90F352
ICCH Input capacity CIN

7 5
25 15
A MB90F352 pF
* : The power supply current is measured with an external clock. 44
MB90350 Series
4. AC Characteristics
(1) Clock Timing (TA = -40 C to +105 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 16 MHz, VSS = AVSS = 0 V) Symbol fC fCL Clock cycle time tCYL tCYLL Input clock pulse width Input clock rise and fall time Internal operating clock frequency (machine clock) PWH, PWL PWHL, PWLL tCR, tCF Pin X0, X1 X0 X0A, X1A X0, X1 X0 X0A, X1A X0 X0A X0 Value Min 3 3 -- 62.5 41.67 10 10 5 Typ 32.768 30.5 15.2 Max 16 24 100 333 333 -- 5 24 fCP 41.67 Internal operating clock cycle time (machine clock) tCP 62.5 tCPL 20 122.1 s 666 ns 1.5 16 fCPL 8.192 50 kHz MHz Unit MHz MHz kHz ns ns s ns s ns Duty ratio is about 30% to 70%. When using external clock When using main clock at TA +105 C When using main clock at TA +125 C When using sub clock When using main clock at TA +105 C When using main clock at TA +125 C When using sub clock Remarks When using an oscillation circuit When using an external clock* When using an oscillation circuit When using an external clock
Parameter
Clock frequency
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned in "Relation among external clock frequency and machine clock frequency".
tCYL
X0
PWH tCF PWL tCR
0.8 VCC 0.2 VCC
tCYLL
X0A
PWHL tCF PWLL tCR
0.8 VCC 0.2 VCC
Clock Timing 45
MB90350 Series
Guaranteed operation range 5.5 4.0 3.5 Guaranteed PLL operation range
Guaranteed A/D Converter operation range
Power supply voltage VCC (V)
1.5
4 Machine clock fCP (MHz)
24
Guaranteed operation range of MB90350 series
Guaranteed oscillation frequency range x6 24 x4 x3 x2 x1
Internal clock fCP (MHz)
16 12 8 4.0 1.5 3 4 8 12 16 24 External clock fC (MHz) * x 1/2 (PLL off)
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz External clock frequency and Machine clock frequency
46
MB90350 Series
(2) Reset Standby Input
(TA = -40 C to +105 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 16 MHz, VSS = AVSS = 0 V) Pin Value Min 500 Max Unit ns s s Remarks Under normal operation In Stop mode, Sub Clock mode, Sub Sleep mode and Watch mode In Main timer mode and PLL timer mode
Parameter
Symbol
Reset input time
tRSTL
RST
Oscillation time of oscillator* + 100 s 100
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators, the oscillation time is between hundreds of s to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation: tRSTL RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operation clock
Oscillation time of oscillator
100 s Oscillation stabilization waiting time Instruction execution
Internal reset
47
MB90350 Series
(3) Power On Reset
(TA = -40 C to +105 C, VCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) (TA = -40 C to +125 C, VCC = 5.0 V 10%, fCP 16 MHz, VSS = AVSS = 0 V) Pin VCC VCC Condition Value Min 0.05 1 Max 30 Unit ms ms Due to repetitive operation Remarks
Parameter Power on rise time Power off time
Symbol tR tOFF
tR 2.7 V 0.2 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. 0.2 V
VCC
VCC 3V VSS
Holds RAM data We recommend a rise of 50 mV/ms maximum.
(4) Clock Output Timing
(TA = -40 C to +105 C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP 24 MHz) Pin CLK CLK Condition Value Min 62.5 41.76 20 13 Max Unit ns ns ns ns Remarks fCP = 16 MHz fCP = 24 MHz fCP = 16 MHz fCP = 24 MHz
Parameter Cycle time CLK CLK
Symbol tCYC tCHCL
tCYC tCHCL
CLK
2.4 V 0.8 V
2.4 V
48
MB90350 Series
(5) Bus Timing (Read) Symbol tLHLL tAVLL ALE ALE, A21 to A16, AD15 to AD00 ALE, AD15 to AD00 A21 toA16, AD15 to AD00, RD A21 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 RD, ALE RD, A21 to A16 A21 to A16, AD15 to AD00, CLK RD, CLK ALE, RD
Parameter ALE pulse width Valid address ALE time ALE Address valid time Valid address RD time Valid address Valid data input RD pulse width RD Valid data input RD Data hold time RD ALE time RD Address valid time Valid address CLK time RD CLK time ALE RD time
(TA = -40C to +105C, VCC = 5.0 V10 %, VSS = 0.0 V, fCP 24 MHz) Value Pin Condition Unit Remarks Min Max tCP/2 - 10 tCP/2 - 20 tCP/2 - 15 tCP - 15 ns ns
tLLAX
ns
tAVRL
ns
tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX
3 tCP/2 - 20 0 tCP/2 - 15 tCP/2 - 10 tCP/2 - 16 tCP/2 - 15 tCP/2 - 15
5 tCP/2 - 60 3 tCP/2 - 50
ns ns ns ns ns ns
tAVCH tRLCH tLLRL
ns ns ns
49
MB90350 Series
tAVCH CLK 2.4 V
tRLCH 2.4 V
tAVLL ALE 2.4 V tLHLL tAVRL RD
tLLAX 2.4 V 0.8 V tRLRH 2.4 V 0.8 V tLLRL
tRHLH 2.4 V
tRHAX A21 to A16 2.4 V 0.8 V tRLDV tAVDV AD15 to AD00 2.4 V 0.8 V 2.4 V Address 0.8 V VIH VIL Read data 2.4 V 0.8 V tRHDX VIH VIL
50
MB90350 Series
(6) Bus Timing (Write)
Parameter
Symbol
(TA = -40C to +105C, VCC = 5.0 V10 %, VSS = 0.0 V, fCP 24 MHz) Value Pin Condition Unit Remarks Min Max A21 to A16, AD15 to AD00, WR WR AD15 to AD00, WR AD15 to AD00, WR A21 to A16, WR WR, ALE WR, CLK tCP-15 3 tCP/2 - 20 3 tCP/2 - 20 15 tCP/2 - 10 tCP/2 - 15 tCP/2 - 15 ns ns ns ns ns ns ns
Valid address WR time WR pulse width Valid data output WR time WR Data hold time WR Address valid time WR ALE time WR CLK time
tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH
tWLCH 2.4 V
CLK
tWHLH ALE 2.4 V
tAVWL WR (WRL, WRH) 0.8 V
tWLWH 2.4 V
tWHAX A21 to A16 2.4 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V 2.4 V Address 0.8 V Write data 2.4 V 0.8 V tWHDX 2.4 V 0.8 V
51
MB90350 Series
(7) Ready Input Timing Symbol tRYHS tRYHH
Parameter RDY setup time RDY hold time
(TA = -40C to +105C, VCC = 5.0 V10 %, VSS = 0.0 V, fCP 24 MHz) Rated Value Test Pin Units Remarks Condition Min Max RDY RDY 45 32 0 ns ns ns fCP = 16 MHz fCP = 24 MHz
Note : If the RDY setup time is insufficient, use the auto-ready function.
CLK
2.4 V
ALE
RD/WR
tRYHS RDY When WAIT is not used. VIH
tRYHH VIH
RDY When WAIT is used.
VIL
52
MB90350 Series
(8) Hold Timing
Parameter Pin floating HAK time HAK time Pin valid time
Symbol tXHAL tHAHV
(TA = -40C to +105C, VCC = 5.0 V10 %, VSS = 0.0 V, fCP 24 MHz) Value Pin Condition Units Remarks Min Max HAK HAK tCP 2 tCP ns 30 tCP ns
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
HAK 0.8V tXHAL Each pin 2.4V 0.8V High-Z
2.4V
tHAHV 2.4V 0.8V
53
MB90350 Series
(9) UART 2/3
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
(TA = -40C to +105C, VCC = 5.0 V10 %, fCP 24 MHz, VSS = 0.0 V) (TA = -40C to +125C, VCC = 5.0 V10 %, fCP 16 MHz, VSS = 0.0 V) Value Pin Condition Unit Remarks Min Max SCK2, SCK3 SCK2, SCK3, SOT2, SOT3 SCK2, SCK3, SIN0 to SIN4 SCK2, SCK3, SIN2, SIN3 SCK2, SCK3 SCK2, SCK3 SCK2, SCK3, SOT2, SOT3 SCK2, SCK3, SIN2, SIN3 SCK2, SCK3, SIN2, SIN3 External clock operation output pins are CL = 80 pF + 1 TTL Internal clock operation output pins are CL = 80 pF + 1 TTL 8 tCP* -80 100 60 4 tCP* 4 tCP* 60 60 +80 150 ns ns ns ns ns ns ns ns ns
* : Refer to " (1) Clock timing" rating for tCP (internal operating clock cycle time). Notes : * AC characteristic in CLK synchronized mode. * CL is load capacity value of pins when testing. * tCP is the machine cycle (Unit : ns)
tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN VIH VIL tSHIX VIH VIL 0.8 V
Internal Shift Clock Mode
54
MB90350 Series
tSLSH SCK VIL tSLOV SOT 2.4 V 0.8 V tIVSH SIN VIH VIL VIL VIH
tSHSL VIH
tSHIX VIH VIL
External Shift Clock Mode
(10) Trigger Input Timing
Parameter
Symbol tTRGH tTRGL
(TA = -40C to +105C, VCC = 5.0 V10 %, fCP 24 MHz, VSS = 0.0 V) (TA = -40C to +125C, VCC = 5.0 V10 %, fCP 16 MHz, VSS = 0.0 V) Value Pin Condition Unit Remarks Min Max INT8 to INT15, INT9R to INT11R, ADTG 5 tCP ns
Input pulse width
VIH
VIH VIL tTRGH tTRGL VIL
INT8 to INT15, INT9R to INT11R, ADTG
55
MB90350 Series
(11) Timer Related Resource Input Timing (TA = -40C to +105C, VCC = 5.0 V10 %, fCP 24 MHz, VSS = 0.0 V) (TA = -40C to +125C, VCC = 5.0 V10 %, fCP 16 MHz, VSS = 0.0 V) Value Parameter Symbol Pin Condition Unit Remarks Min Max tTIWH Input pulse width tTIWL TIN1, TIN3, IN0, IN1, IN4 to IN7 4 tCP ns
VIH
VIH VIL tTIWH tTIWL VIL
TIN1, TIN3, IN0, IN1, IN4 to IN7
(12) Timer Related Resource Output Timing (TA = -40C to +105C, VCC = 5.0 V10 %, fCP 24 MHz, VSS = 0.0 V) (TA = -40C to +125C, VCC = 5.0 V10 %, fCP 16 MHz, VSS = 0.0 V) Value Parameter Symbol Pin Condition Unit Remarks Min Max CLK TOUT change time tTO TOT1, TOT3, PPG4, PPG6, PPG8 to PPGF 30 ns
CLK
2.4 V
TOT1, TOT3, PPG4, PPG6 PPG8 to PPGF
tTO
2.4 V 0.8 V
56
MB90350 Series
(13) I2C Timing
(TA = -40C to +105C, VCC = AVCC = 5.0 V10 %, fCP 24 MHz, VSS = AVSS = 0.0 V) (TA = -40C to +125C, VCC = AVCC = 5.0 V10 %, fCP 16 MHz, VSS = AVSS = 0.0 V) Standard-mode Fast-mode*4 Unit Parameter Symbol Condition Min Max Min Max fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS R = 1.7 k, C = 50 pF*1 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 100 3.45*2 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 400 0.9*3 kHz s s s s s ns s s
SCL clock frequency Hold time (repeated) START condition SDASCL "L" width of the SCL clock "H" width of the SCL clock Set-up time for a repeated START condition SCLSDA Data hold time SCLSDA Data set-up time SDASCL Set-up time for STOP condition SCLSDA Bus free time between a STOP and START condition
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT have only to be met if the device does not stretch the "L" width (tLOW) of the SCL signal. *3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA tBUS
tLOW SCL
tSUDAT
tHDSTA
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
57
MB90350 Series
5. A/D Converter
(TA = -40 C to +105 C, 3.0 V AVRH, VCC = AVCC = 5.0 V 10%, fCP 24 MHz, VSS = AVSS = 0 V) (TA = -40 C to +125 C, 3.0 V AVRH, VCC = AVCC = 5.0 V 10%, fCP 16 MHz, VSS = AVSS = 0 V) Symbol VOT VFST IAIN VAIN IA IAH IR IRH Pin AN0 to AN14 Value Min AVSS - 1.5 Typ AVSS + 0.5 Max 10 3.0 2.5 1.9 AVSS + 2.5 Unit bit LSB LSB LSB LSB Remarks
Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage current Offset between input channels
AN0 to AN14 AVRH - 3.5 AVRH - 1.5 AVRH + 0.5 LSB AN0 to AN14 AN0 to AN14 AVRH AVCC AVCC AVRH AVRH AN0 to AN14 1.0 2.0 0.5 1.2 -0.3 AVSS AVSS + 2.7 3.5 600 16,500 s s A V V mA A A A LSB * * 4.5 V AVCC 5.5 V 4.0 V AVCC < 4.5 V 4.5 V AVCC 5.5 V 4.0 V AVCC < 4.5 V
+0.3 AVRH AVCC 7.5 5 900 5 4
* : IF A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) . Note : The accuracy gets worse as |AVRH - AVSS| becomes smaller.
58
MB90350 Series
6. Definition of A/D Converter Terms
Resolution Non linearity error Differential linearity error Total error Zero reading voltage Full scale reading voltage : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( "00 0000 0000" "00 0000 0001" ) and full-scale transition line ( "11 1111 1110" "11 1111 1111" ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. : Input voltage which results in the minimum conversion value. : Input voltage which results in the maximum conversion value.
Total error
3FF 3FE 3FD Digital output {1 LSB x (N - 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB
004 003 002 001 0.5 LSB AVSS Analog input
VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics
AVRH
Total error of digital output "N" =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVRH - AVSS 1 LSB = (Ideal value) [V] 1024 VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVRH - 1.5 LSB [V]
[LSB]
VNT : A voltage at which digital output transitions from (N - 1) to N.
(Continued)
59
MB90350 Series
(Continued)
Non linearity error
3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB x (N - 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics
Differential linearity error
Ideal characteristics
Digital output
N
004 003 002
N-1
V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Analog input
Ideal characteristics 001 VOT (actual measurement value) AVSS Analog input AVRH
N-2
AVSS
Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N+1) T - VNT 1 LSB VFST - VOT 1022 -1 LSB [LSB] [V]
[LSB]
VOT : Voltage at which digital output transits from "000H" to "001H." VFST : Voltage at which digital output transits from "3FEH" to "3FFH."
60
MB90350 Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs : Recommended output impedance of external circuits are : Approx. 1.5 k or lower (4.0 V AVCC 5.5 V, sampling period 0.5 s) If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. * Analog input circuit model
Analog input R Comparator
C
4.5 V AVCC 5.5 V : R = 2.52 k, C = 10.7 pF : : 4.0 V AVCC < 4.5 V : R = 13.6 k, C = 10.7 pF : :
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics
Parameter Sector erase time Chip erase time Word (16 bit width) programming time Program/Erase cycle Flash Data Retention Time Average TA = +85 C TA = +25 C VCC = 5.0 V Conditions Value Min 10,000 20 Typ 1 9 16 Max 15 3,600 Unit s s s cycle Years * Remarks Excludes programming prior to erasure Excludes programming prior to erasure Except for the overhead time of the system
* : This value comes from the technology qualification. (Using Arrhenius equation to translate high temperature measurements into normalized value at +85 C)
61
MB90350 Series
s ORDERING INFORMATION
Part number MB90F352PFM MB90F352SPFM MB90352PFM MB90352SPFM MB90V340A-101 MB90V340A-102 Package 64-pin Plastic LQFP (FPT-64P-M09) 64-pin Plastic LQFP (FPT-64P-M09) 299-pin Ceramic PGA (PGA-299C-A01) For evaluation Remarks
62
MB90350 Series
s PACKAGE DIMENSIONS
64-pin Plastic LQFP (FPT-64P-M09) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness including plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
14.000.20(.551.008)SQ
* 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches) Note : The values in parentheses are reference values.
63
MB90350 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0405 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of MB90F352

	To Download MB90F352 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .